* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 * Component Design by Example ', 2001 ISBN 0-970 * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-970 * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-970 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712 Initial begin for ( int i = 0 i < 1024 i ++ )ĭata_mem = ' 0 // <- written HERE, the violation end assign data_read = data_mem always_ff ( posedge (clk ) ) begin if (data_req.we )ĭata_mem <= data_write // And written here endįor training, consulting, services: contact Tag_mem = ' 0 end assign tag_read = tag_mem always_ff ( posedge (clk ) ) begin if (tag_req.we ) ) input bit clk input cache_req_type tag_req //tag request input cache_tag_type tag_write //write port output cache_tag_type tag_read //read portĬache_tag_type tag_mem initial begin for ( int i = 0 i < 1024 i ++ ) ) input bit clk input cache_req_type data_req //data request input cache_data_type data_write //write port (128-bit line) output cache_data_type data_read //read portĬache_data_type data_mem initial begin for ( int i = 0 i < 1024 i ++ )ĭata_mem = ' 0 end assign data_read = data_mem always_ff ( posedge (clk ) ) begin if (data_req.we )ĭata_mem <= data_write end endmodule //cache: tag memory, single port, 1024 blocks module dm_cache_tag ( Cache: data memory, single port, 1024 blocks import cache_def ::* timeunit 1ns timeprecision 1ps module dm_cache_data (clk ,

Modelsim vlog